The present invention relates to a parallel connection of a plurality of flat type semiconductor switches which enables the semiconductor switches to switch ON and OFF simultaneously at high speed without causing significant switching time differences.
Semiconductor switches facilitate easy and smooth DC to AC or AC to DC electric power conversion. However, a single semiconductor switch has a limited capacity which limits the wattage of electric power convertible by a semiconductor switch. Therefore, the power conversion capacity of a semiconductor switching apparatus is increased by connecting many semiconductor switches in parallel.
Referring to FIG. 6, a prior art semiconductor switch 2 includes a drain electrode D, a gate electrode G, and a source electrode S, all on a substrate.
Referring now to FIG. 5, three semiconductor switches 2a, 2b, 2c, of the type shown in FIG. 6, are connected in parallel. In the prior art, drain electrodes D of all three semiconductor switches 2a, 2b and 2c are connected in common to a drain line 6. Source electrodes S are connected in common to a source line 7. Since power conversion requires semiconductor switches 2a, 2b, 2c to switch ON and OFF simultaneously, gate electrodes G of semiconductor switches 2a, 2b, 2c are connected in common to a gate line 8. Source line 7 and gate line 8 are connected with a gate drive circuit 5.
Gate drive circuit 5 applies an ON-voltage between gate electrode G and source electrode S, thereby causing an ON-current to flow from gate electrode G to source electrode S of each of semiconductor switches 2a, 2b, 2c and causing semiconductor switches 2a, 2b, 2c to turn ON simultaneously. When gate drive circuit 5 stops applying the ON-voltage or applies a voltage of opposite polarity to the ON-voltage between the gate electrode and the source electrode, an OFF-current flows from source electrode S to gate electrode G of each of semiconductor switches 2a, 2b, 2c causing semiconductor switches 2a, 2b, 2c to turn OFF simultaneously.
When gate drive circuit 5 and semiconductor switches 2a, 2b, 2c are connected as shown in FIG. 5, a length of gate line 8 between gate drive circuit 5 and gate electrode G of semiconductor switch 2b is longer than a line length between gate drive circuit 5 and gate electrode G of semiconductor switch 2a. In addition, a line length between gate drive circuit 5 and gate electrode G of semiconductor switch 2c is much longer than the line length between gate drive circuit 5 and gate electrode G of semiconductor switch 2a.
For example, when the line length between the gates of neighboring semiconductor switches is several tens of centimeters, wiring inductance L of the gate line and source line is several hundred nil. Static capacitance C of the gate of a large capacity semiconductor switch of several hundred amps and several hundred volts is several hundreds nF. A transmission delay time of a signal (ON-current) from gate drive circuit 5 between neighboring gate electrodes is almost proportional to a root of a product of the wiring inductance L and the static gate capacitance C. Therefore, when a number of semiconductor switches are connected in parallel with wiring inductance L and static gate capacitance C are in the above stated ranges of inductance and capacitance, the transmission delay time is several hundreds of nanoseconds.
Since the wiring inductance L causes signal transmission delay between semiconductor switches, such as, for example, semiconductor switches 2a and 2c in the parallel circuit of FIG. 5, the signal transmission delay causes a further time difference of several hundred nanoseconds or more in the ON-OFF operations of the switches. In the transition from ON to OFF, turn-off current localizes to that semiconductor switch which switches OFF later than the others. The turn-off loss therefore localizes to this delaying semiconductor switch. In transition from OFF to ON, turn-on current localizes to that semiconductor switch which switches ON earlier than the others.
Since the losses localize to particular semiconductor switches if the time difference exists in ON-OFF operation, it is meaningless to connect many semiconductor switches in parallel. If many semiconductor switches are connected in parallel, convertible electric power fails to increase as much as intended. Using a thick gate line to reduce wiring inductance L requires additional space for wiring and connection. In addition, connecting thick lines is not easy. Since the inductance of the main circuit conductors (anode side wiring and cathode side wiring) in a semiconductor switching apparatus for high electric power conversion should be small, it is not allowable to leave a space around the semiconductor switches through which excessive magnetic flux passes. Thus, room is needed for screw-type or soldering connections.